Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums

Soft errors due to alpha particles, neutrons and environmental noise are of serious concern in highly scaled CMOS circuits. This mandates the use of error/noise tolerance mechanisms in circuit design. Prior work has addressed error correction and compensation techniques for linear digital systems using checksum codes. However no low-cost checksum based technique is found in the literature for nonlinear digital signal processing systems. The problem of error detection and compensation in nonlinear systems is harder due to difficulties in encoding nonlinear operations and correcting for errors in the same. This paper presents a checksum based technique for error compensation in nonlinear digital filters using the time-freeze linearization method. The technique uses distance-two linearized checksum error detection codes for SNR improvement using probabilistic error compensation instead of deterministic error removal. It is shown that by careful checksum code design, significant filter SNR improvement can be obtained in the presence of soft errors.