A switched-capacitor interface circuit for integrated sensor applications

Author

Chan, P.K. ; Zhang, H.L.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

372

Abstract

A new switched-capacitor interface circuit with differential-input single-ended output (DISO) for integrated sensor applications is presented. The circuit adopts the correlated double sampling technique combined with the auxiliary amplifier structure to cancel the 1/f noise and to minimize the systematic offset and errors due to charge injection. The simulated results show that the circuit exhibits a DC offset of 7 μV and consumes 620 μA at a single 5 V supply, with a sample rate 128 kHz in 0.8 μm CMOS technology

Keywords

CMOS integrated circuits; capacitive sensors; detector circuits; switched capacitor networks; 0.8 micron; 1/f noise; 128 kHz; 5 V; 620 muA; CMOS switched capacitor interface circuit; DC offset; auxiliary amplifier; charge injection; correlated double sampling; differential-input single-ended output; integrated capacitive sensor; Acceleration; Capacitive sensors; Capacitors; Circuit simulation; Frequency; Mechanical sensors; Operational amplifiers; Parasitic capacitance; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921870

Filename

921870