DocumentCode
3083780
Title
A systematic approach for Failure Modes and Effects Analysis of System-On-Chips
Author
Mariani, Riccardo ; Boschi, Gabriele
Author_Institution
YOGITECH SpA, Pisa
fYear
2007
fDate
8-11 July 2007
Firstpage
187
Lastpage
188
Abstract
This paper proposes a method to perform failure mode and effects analysis (FMEA) on system-on- chips (SoC). An automatic tool extracts information from the SoC description and uses them to estimate the intrinsic criticality of invariant and elementary "sensitive zones " and to compute metrics such failure rates, safe failures fraction and diagnostic coverage. A validation flow based on fault injection and fault simulation is included to cross check the FMEA.
Keywords
failure analysis; fault diagnosis; fault simulation; system-on-chip; FMEA; SoC; automatic tool; diagnostic coverage; elementary sensitive zones; failure modes and effects analysis; failure rates; fault injection; fault simulation; intrinsic invariant criticality; safe failures fraction; system-on-chips; systematic approach; validation flow; Circuit analysis; Circuit faults; Circuit simulation; Data mining; Databases; Failure analysis; IEC standards; Performance analysis; Safety; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2007. IOLTS 07. 13th IEEE International
Conference_Location
Crete
Print_ISBN
0-7695-2918-6
Type
conf
DOI
10.1109/IOLTS.2007.10
Filename
4274843
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