Title :
Highly Reliable Power Aware Memory Design
Author :
Argyrides, Costas ; Pradhan, Dhiraj K.
Author_Institution :
Univ. of Bristol, Bristol
Abstract :
In this paper, an efficient technique for designing RAMs for on chip correction of double errors integrated on H-tree memory architecture is discussed. The reliability of the proposed design is improved by 8X while the Mean Time To Failure is improved 3X while comparing to traditional Hamming codes for a 256 Mbits memory chip. The area is sacrificed for these reliability improvements, significant power savings and the performance boost.
Keywords :
Hamming codes; integrated circuit design; integrated memory circuits; random-access storage; H-tree memory architecture; Hamming codes; RAM; power aware memory design; Capacitance; Computer science; Energy consumption; Error correction; Error correction codes; Hardware; Microprocessors; Random access memory; Read-write memory; Threshold voltage;
Conference_Titel :
On-Line Testing Symposium, 2007. IOLTS 07. 13th IEEE International
Conference_Location :
Crete
Print_ISBN :
0-7695-2918-6
DOI :
10.1109/IOLTS.2007.37
