ASIC implementation of AES

This paper proposes a low power implementation of rolled architecture for AES encryption and decryption. The design employs key expansion for all the three standard key lengths of 128, 192 and 256 bits. The keys are expanded once and stored in a memory while the encryption process is carried out. We have used 180nm standard cell library to implement the design. The design was clocked at 125 MHz to obtain a throughput of 1.6Gbps for 128 bit key, 1.33Gbps for 192 bit key and 1.14Gbps for 256 bit key. In total, 58445 gates were employed to implement all key size encryption, decryption and key expansion with a very low power consumption of 22.85mW.