DocumentCode
3084003
Title
A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits
Author
Gardiner, K.T. ; Yakovlev, A. ; Bystrov, A.
Author_Institution
Univ. of Newcastle upon Tyne, Newcastle upon Tyne
fYear
2007
fDate
8-11 July 2007
Firstpage
223
Lastpage
230
Abstract
A technique of constructing dual-rail muller pipelines tolerant to transient faults is proposed. The pipeline datapath is either an NCL-D or NCL-X circuit. A dedicated controller implements the error recovery protocol, which significantly improves fault tolerance with respect to the earlier rail synchronization method. A case study featuring transient fault simulation is presented.
Keywords
asynchronous circuits; fault tolerance; flip-flops; synchronisation; C-element latch scheme; NCL-D circuit; NCL-X circuit; asynchronous circuits; dual-rail Mutter pipelines tolerant; error recovery protocol; rail synchronization method; transient fault tolerance; Asynchronous circuits; Circuit faults; Delay; Fault tolerance; Latches; Logic testing; Pipelines; Pulse circuits; Rails; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2007. IOLTS 07. 13th IEEE International
Conference_Location
Crete
Print_ISBN
0-7695-2918-6
Type
conf
DOI
10.1109/IOLTS.2007.5
Filename
4274855
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