DocumentCode :
3084048
Title :
A new distributed event-driven gate-level HDL simulation by accurate prediction
Author :
Kim, Dusung ; Ciesielski, Maciej ; Yang, Seiyang
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
4
Abstract :
This paper describes a new and efficient solution to a distributed event-driven gate-level HDL simulation. It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual local modules in local simulations, derived from a model at a higher abstraction level (RTL). Using the predicted rather than actual signal values makes it possible to eliminate or greatly reduce the communication and synchronization overhead in a distributed event-driven simulation.
Keywords :
discrete event simulation; hardware description languages; parallel processing; distributed event driven gate level HDL simulation; higher abstraction level; signal value prediction; spatial parallelism; Computational modeling; Hardware design languages; Logic gates; Object oriented modeling; Predictive models; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763280
Filename :
5763280
Link To Document :
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