Title :
Teaching pipelining and concurrency using hardware description languages
Author :
Huang, Tsai Chi ; Yalamanchili, Sudhakar ; Melton, Roy W. ; Bingham, Philip R. ; Alford, Cecil O.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Relating to a previous simplified VHDL processor model, a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, USA. This paper first describes the pipeline processor model and its VHDL implementation. It then presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students
Keywords :
computer architecture; computer science education; concurrency theory; educational courses; hardware description languages; pipeline processing; teaching; USA; computer architecture course; concurrency teaching; hardware description languages; implementation extensions; pipelining teaching; students; synthesized VHDL pipeline microprocessor model; university; Computer architecture; Concurrent computing; Decoding; Education; Hardware design languages; Identity-based encryption; Logic devices; Microprocessors; Pipeline processing; Registers;
Conference_Titel :
Microelectronic Systems Education, 1999. MSE'99. IEEE International Conference on
Conference_Location :
Arlington, VA
Print_ISBN :
0-7695-0312-8
DOI :
10.1109/MSE.1999.787035