DocumentCode
3084109
Title
A study for branch predictors to alleviate the aliasing problem [pipelining]
Author
Xie, Tieling ; Evans, Robert ; Chu, Yul
Author_Institution
Electr. & Comput. Eng. Dept., Mississippi State Univ., MS, USA
fYear
2005
fDate
8-10 April 2005
Firstpage
603
Lastpage
608
Abstract
Modern processors usually have a deep pipeline, superscalar architecture to obtain higher performance. As pipelines are getting deeper, accurate branch prediction is critical to achieve high performance, since fetched instructions after a branch have to be flushed from inside the pipeline when the prediction is wrong. This paper studies the performance of several types of branch predictors, starting from local branch predictor and global branch predictor. Simulation results show that the global history predictor outperforms the local history predictor due to the characteristic that branches tend to be correlated. However, the global history predictor still suffers an aliasing problem that degrades performance. Four techniques are proposed to alleviate the aliasing problem. The performance is evaluated by using Simplescalar with SPEC CINT95 benchmark programs. The proposed predictors display better performance over the conventional predictors after careful configuration of each.
Keywords
parallel architectures; pipeline processing; aliasing; branch prediction; correlated branches; deep pipeline superscalar architecture; global branch predictor; global history predictor; local branch predictor; pipelining; processors; wrong prediction fetched instruction flushing; Accuracy; Computer architecture; Degradation; Displays; High performance computing; History; Microprocessors; Parallel processing; Pipeline processing; Predictive models;
fLanguage
English
Publisher
ieee
Conference_Titel
SoutheastCon, 2005. Proceedings. IEEE
Print_ISBN
0-7803-8865-8
Type
conf
DOI
10.1109/SECON.2005.1423313
Filename
1423313
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