Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips

We describe a self-configuration methodology to tolerate defective nodes in chips organized in massively replicative architectures as those shown below in Figure 1, made up of hundreds of cores in a highly defective technology. Note that the keyword of this presentation is not configuration but self-configuration. The basic idea is that chips will become so complex that it will be unrealistic to consider diagnosing all nodes and all routes with some external equipment. Contrarily, chips should become autonomous and adaptative to preserve their resilience, and as little external interventions as possible should be involved to control the start up phase and the subsequent operation. By self-configuration we mean self-diagnosis of cores through mutual tests (both at startup and possibly at runtime), self-configuration of communications, self-shutdown of the cores which cannot take part to the processing, and ultimately, adaptative task allocation and redundant execution at runtime to cope with transient faults.