Title :
Two methods for 24 Gbps test signal synthesis
Author :
Keezer, D.C. ; Gray, C.E.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper describes and compares two methods for producing digital test signals up to 24 Gbps. Prototypes are experimentally characterized to determine signal quality, and the two methods are demonstrated and compared. The residual timing errors are dominated by jitter. Typical random jitter (RJ) is about 1.17ps to 1.4ps (RMS) including system measurement errors for the two methods. Deterministic Jitter (DJ) is between 2.4ps and 8.5ps. Total jitter (TJ) ranges between 18.9ps and 28.2ps at a bit-error-rate BER=10-12.
Keywords :
automatic test equipment; circuit noise; circuit testing; error statistics; jitter; signal generators; signal synthesis; bit error rate; bit rate 24 Gbit/s; digital test signal; random jitter; residual timing error; signal quality; system measurement error; test signal synthesis; total jitter; Built-in self-test; Clocks; Indium phosphide; Jitter; Logic gates; Multiplexing; Timing; ATE; Jitter; Test Synthesis; multi-Gbps;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
Print_ISBN :
978-1-61284-208-0
DOI :
10.1109/DATE.2011.5763288
