DocumentCode
3084358
Title
A scalable resistor-less PLL design for PowerPCTM microprocessors
Author
Alvarez, Jose ; Sanchez, Hector ; Countryman, Roger ; Alexander, Mike ; Nicoletta, Carmine ; Gerosa, Gianfranco
Author_Institution
Motorola Inc., Austin, TX, USA
fYear
1996
fDate
7-9 Oct 1996
Firstpage
293
Lastpage
300
Abstract
A new resistor-less phase locked loop implemented in a 2.5 V, 0.35 μm, CMOS technology is described. The design supports 13 different clock multiplier settings and uses a current-controlled-oscillator along with switched current sources to adjust the clock phase. Practical issues concerning system design and PLL stability parameters are also discussed. Simulation and characterization results show the response of the PLL to power supply and input clock modulation
Keywords
CMOS integrated circuits; constant current sources; microprocessor chips; oscillators; phase locked loops; 0.35 micron; 2.5 V; CMOS technology; PowerPC microprocessors; characterization results; clock multiplier settings; current-controlled-oscillator; input clock modulation; phase locked loop; power supply; scalable resistor-less PLL design; simulation; stability parameters; switched current sources; system design; CMOS technology; Capacitors; Clocks; Filters; Frequency modulation; Isolation technology; Jitter; Microprocessors; Phase locked loops; Power supplies;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-7554-3
Type
conf
DOI
10.1109/ICCD.1996.563570
Filename
563570
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