An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver

A 3 V 8-bit 200 MSPS CMOS folding/interpolation A/D converter for analog interface module of TFT-LCD Driver is proposed. It is composed of both a coarse ADC and a fine ADC whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (interpolation Rate) is 8, respectively. For the purpose of improving SNDR, distributed track-and-hold circuits are included at the input stage. In order to obtain a high speed operation and low power consumption, further, a novel analog latch and digital encoder based on a fast compression algorithm are proposed. The chip has been fabricated with a 0.35 μm 2-poly 3-metal CMOS technology. The effective chip area is about 1.2 mm×0.8 mm and it dissipates about 210 mW at 3 V power supply. The INL and DNL are within 1 LSB, respectively. The SNDR is about 43 dB, when the input frequency reaches 10 MHz at 200 MHz clock frequency