Title :
Managing the interconnect continuum...from silicon to package and board
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
As VLSI technologies advance and performance of logic chips approaches 1 GHz, it is recognised that their performance is limited by the interconnect system. Furthermore, it is not just the interconnects on the chip but the entire interconnect continuum from the chip, through the package and the system board. In this paper, we present a holistic view of the challenges and potential directions for this interconnect continuum. It is seen that performance can be affected by architecture and partitioning of the chips and the systems. Additionally, the advent of new interconnect technologies such as copper metallization, flip-chip and organic substrates play key roles in managing and optimizing the outcome
Keywords :
VLSI; flip-chip devices; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; integrated logic circuits; 1 GHz; Cu; Si; VLSI technology; board interconnect; chip architecture; chip interconnects; chip partitioning; copper metallization; flip-chip; interconnect continuum; interconnect system; interconnect technologies; logic chip performance; logic chips; organic substrates; package interconnect; system board; Clocks; Computer architecture; Copper; Integrated circuit interconnections; Logic; Packaging; Power system interconnection; Silicon; Transistors; Very large scale integration;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787061
