Title :
Optimum chip clock distribution networks
Author :
Zarkesh-Ha, Payman ; Meindl, James D.
Author_Institution :
Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Clock skew, clock signal degradation (attenuation) and power dissipation are the three main concerns in designing a chip clock distribution network. Two new design planes, utilizing compact models for clock skew, clock signal degradation and power dissipation are proposed. An example of a 0.18 μm CMOS technology shows that the maximum clock frequency of 610 MHz for a typical 2×2 cm2 chip design can be achieved by using 4 levels of H-tree
Keywords :
CMOS integrated circuits; clocks; delays; integrated circuit design; integrated circuit modelling; timing; 0.18 micron; 2 cm; 610 MHz; CMOS technology; H-tree levels; attenuation; chip clock distribution network design; chip clock distribution networks; chip design; clock signal degradation; clock signal degradation model; clock skew; clock skew model; design planes; maximum clock frequency; optimum chip clock distribution networks; power dissipation; power dissipation model; CMOS technology; Clocks; Degradation; Driver circuits; Integrated circuit interconnections; Power dissipation; Power system interconnection; Power system modeling; Semiconductor device modeling; Signal design;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787065
