Impact of interconnect architecture on chip size and die yield

Author

Liu, Ruichen ; Pai, Chien-Shing ; Cong, Hong-Ih ; Lai, Warren ; Martinez, Emilio

Author_Institution

Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA

fYear

1999

fDate

1999

Firstpage

21

Lastpage

23

Abstract

Interconnecting 200 million transistors in high performance logic circuits requires several kilometers of wires at the 100 nm technology node for which volume production is only seven years away. In order to reduce the interconnect RC delay, the interconnect pitches must be larger than minimum scaling except for the lowest levels, even when Cu and low-k dielectric are used. The larger pitches result in increased die size and/or more levels of interconnects, both of which adversely affect die yield. This work quantifies the impact on die yield for various interconnect approaches

Keywords

dielectric thin films; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; integrated logic circuits; 100 nm; Cu/low-k dielectric interconnects; chip size; die size; die yield; interconnect RC delay; interconnect architecture; interconnect levels; interconnect pitch; logic circuits; minimum scaling; technology node; transistors; volume production; Conductors; Delay; Dielectrics; Integrated circuit interconnections; Logic circuits; Microprocessor chips; Production; Shape; Wire; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology, 1999. IEEE International Conference

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-5174-6

Type

conf

DOI

10.1109/IITC.1999.787066

Filename

787066