Title :
Interconnect performance modeling for 3D integrated circuits with multiple Si layers
Author :
Souri, Shukri J. ; Saraswat, Krishna C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
Long interconnect RC delay is increasing rapidly with chip size, limiting chip performance. 3D device integration in multiple layers of Si promises to increase transistor packing density and reduce RC time delay through reducing chip size. This paper offers a quantitative approach to compare current technology chip performance to that of 3D ICs
Keywords :
delays; elemental semiconductors; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; semiconductor thin films; silicon; 3D ICs; 3D device integration; 3D integrated circuits; RC time delay; Si; chip performance; chip size; interconnect RC delay; interconnect performance modeling; multiple Si layers; transistor packing density; Delay effects; Delay estimation; Equations; Integrated circuit interconnections; Integrated circuit modeling; Joining processes; Logic; Stochastic processes; Three-dimensional integrated circuits; Wiring;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787067
