Design tradeoffs and experience with Motorola PowerPC migration tools

Author

Breternitz, M. ; Manikonda, A. ; Ommerman, M. ; Su, W. ; Thornton, A.

Author_Institution

RISC Software Div., Motorola Inc., Austin, TX, USA

fYear

1996

fDate

7-9 Oct 1996

Firstpage

301

Lastpage

308

Abstract

The Motorola PowerPC migration tools enable the conversion of assembly programs from other architectures to PowerPC. This paper describes the design approach and experience with the tool to translate x86 assembly programs to PowerPC. The key problems of handling 16-bit code, the effects of masking 16-bit operations into 32-bit registers and optimization of condition flags are discussed. The efficiency of translation and the effects of architectural constraints on design tradeoffs are analyzed

Keywords

computer architecture; microprocessor chips; program assemblers; program interpreters; reduced instruction set computing; 16-bit code; 16-bit operations; 32-bit registers; Motorola PowerPC migration tools; architectural constraints; assembly programs; condition flags; design tradeoffs; x86 assembly programs translation; Application software; Assembly; Computer architecture; Emulation; Operating systems; Optimizing compilers; Read only memory; Reduced instruction set computing; Runtime; Software tools;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-7554-3

Type

conf

DOI

10.1109/ICCD.1996.563571

Filename

563571