Title :
Al deposition temperature process window for 0.20 μm Al RIE interconnections
Author :
Clevenger, L.A. ; Honda, Masakazu ; Ravikumar, R. ; Stojakovic, George
Author_Institution :
DRAM Dev. Alliance, IBM Microelectron., Hopewell Junction, NY
Abstract :
As VLSI dimensions decrease to below 0.2 μm, BEOL processing requirements are becoming more stringent. Al conductor line widths and pitches are becoming smaller and aspect ratios are increasing in order to meet design requirements. At the same time, process windows for producing these BEOL wires are becoming more difficult to maintain. This paper focuses on the process window for Al(Cu) deposition temperature for a 0.2 μm wide, 0.44 μm pitch, Al RIE interconnection used in a 256 Mbit DRAM. While surface roughness and Al texture degrade slightly with increasing deposition temperature, other properties like RIE etchability, Θ-Al2Cu participate distribution and texture, sheet resistance and opens/shorts yield either improve or are unaffected as the Al deposition temperature is increased. All of these parameters combine to suggest a wide process window for Al deposition temperature for 0.2 μm Al RIE interconnections
Keywords :
DRAM chips; VLSI; aluminium alloys; copper alloys; electric resistance; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; sputter etching; surface texture; surface topography; thermal analysis; 0.2 micron; 0.44 micron; 256 Mbit; Al RIE interconnections; Al conductor line width; Al conductor pitch; Al deposition temperature; Al deposition temperature process window; Al texture; Al(Cu) deposition temperature; Al2Cu; AlCu; BEOL processing; BEOL wires; DRAM; RIE etchability; VLSI dimensions; aspect ratios; deposition temperature; design requirements; opens yield; process windows; sheet resistance; shorts yield; surface roughness; theta-Al2Cu participate distribution; theta-Al2Cu participate texture; Conductors; Degradation; Random access memory; Rough surfaces; Surface resistance; Surface roughness; Surface texture; Temperature distribution; Very large scale integration; Wires;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787068