Analysis of interconnect delay for 0.18 μm technology and beyond

In this paper, several interconnect schemes are investigated in terms of RC delay. An inverter ring oscillator with a three-line three-section RC interconnect model is used for this study. It is shown that a dual damascene Cu interconnect with lower k-value anti-diffusion layer such as SiBON (k=3.9) can out-perform Al-based interconnects for the same conductor thickness, when intra- and inter-metal dielectrics of similar k-value are used. In addition, when using Cu with 60% of Al thickness, the dual damascene Cu/USG has better interconnect delay performance than even Al/HSQ for narrow metal spacing. Guidelines for dual damascene Cu interconnect optimization can be obtained through the sensitivity study of interconnect process parameters on RC delay presented here