A novel Hspice macro model for the ESD behavior of gate grounded NMOS and gate coupled NMOS

In this paper an Hspice macro model is presented to model the snapback characteristics of GGNMOS (gate-grounded NMOS) and GCNMOS (gate-coupled NMOS) under ESD stress. The 5V NMOS be simulated in this paper is based on the 0.35um BCD technology as an ESD protection device. The new macro model has successfully predicted the trigger voltage and holding voltage of the GGNMOS and GCNMOS according to the silicon data. The effects of device parameters Tref and Rs exhibit a good trend curve in agreement with BJT model, which helps for the prediction of the trigger voltage and holding voltage for ESD circuit application.