A novel Hspice macro model for the ESD behavior of gate grounded NMOS and gate coupled NMOS

Author

Shao Ming Yang ; Hema, Ep ; Gene Sheu ; Mrinal, Aryadeep ; Amanullah, Md ; Pa Chen

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan

fYear

2015

fDate

15-16 March 2015

Firstpage

1

Lastpage

3

Abstract

In this paper an Hspice macro model is presented to model the snapback characteristics of GGNMOS (gate-grounded NMOS) and GCNMOS (gate-coupled NMOS) under ESD stress. The 5V NMOS be simulated in this paper is based on the 0.35um BCD technology as an ESD protection device. The new macro model has successfully predicted the trigger voltage and holding voltage of the GGNMOS and GCNMOS according to the silicon data. The effects of device parameters Tref and Rs exhibit a good trend curve in agreement with BJT model, which helps for the prediction of the trigger voltage and holding voltage for ESD circuit application.

Keywords

MOSFET; SPICE; electrostatic discharge; ESD behavior; GCNMOS; GGNMOS; Hspice macro model; gate coupled NMOS; gate grounded NMOS; holding voltage; size 0.35 mum; snapback characteristics; trigger voltage; voltage 5 V; Data models; Electrostatic discharges; Fitting; Integrated circuit modeling; Logic gates; MOS devices; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Technology International Conference (CSTIC), 2015 China

Conference_Location

Shanghai

ISSN

2158-2297

Type

conf

DOI

10.1109/CSTIC.2015.7153335

Filename

7153335