A scaling scheme and optimization methodology for deep sub-micron interconnect

In this paper we study the requirements for interconnect in deep-submicron technologies and identify critical factors that will require innovations in process technology, process integration and circuit-and-system design techniques. We also describe a scaling scheme for global lines to optimize the interconnect for a given application domain such as microprocessors, ASIC´s or memory. For local interconnect we demonstrate that cross-talk is the major challenge which can be addressed by selectively using larger drivers to reduce cross-talk noise when necessary. An interconnect system optimization methodology is also presented that can be used to determine the geometry parameters of a multi-level interconnect system based on the criterion for performance and reliability