DocumentCode
3085054
Title
A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations
Author
Smith, Brad ; Blackley, Scott ; Carter, Rusty ; Chheda, Sejal ; Crabtree, Phil ; Farber, David ; Gall, Martin ; Islam, Rabiul ; Jawarani, Dharmesh ; King, Charlie ; Menke, Doug ; Nelson, Richard ; Pressley, Laura ; Smith, David ; Sparks, Terry ; Stephens,
Author_Institution
Network & Comput. Syst. Group, Motorola Inc., Austin, TX, USA
fYear
1999
fDate
1999
Firstpage
106
Lastpage
108
Abstract
A comparison of via overetch is made between a conventional integration using aluminum interconnects plus tungsten via plugs and a dual-inlaid integration using copper. Excessive overetch for Al interconnects can cause reliability problems because of veil formation, as well as create very high aspect ratio recesses that are difficult to fill. The reasons for variation in interlevel dielectric (ILD) thickness and via etch rate are discussed. For the Al-W interconnect system, oxide CMP controls the ILD thickness. In addition, the via etch rate has been observed to drop over time. Both contribute significant variations to via overetch. For a via-first dual-inlaid integration, the ILD deposition determines the via depth uniformity. In metal-first dual-inlaid, the metal trench etch controls the via depth. In both cases, the via etch rate has been optimized to be more stable over time. Overall, the Al-W integration has a very wide range of via depths and etch rates that must be tolerated, whereas the dual-inlaid integrations have only a few percent of variation
Keywords
aluminium; copper; dielectric thin films; etching; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; tungsten; Al interconnects; Al-W; Al-W integration; Al-W interconnect system; Cu; Cu dual-inlaid integration; ILD deposition; ILD thickness; aluminum interconnects; dual-inlaid copper integration; interlevel dielectric thickness; metal trench etch; metal-first dual-inlaid integration; oxide CMP; recess aspect ratio; reliability; tungsten via plugs; veil formation; via depth; via depth uniformity; via etch rate; via etch rate optimization; via etch rate stability; via overetch; via overetch variations; via-first dual-inlaid integration; Aluminum; Artificial intelligence; Copper; Dielectrics; Etching; Integrated circuit interconnections; Random processes; Thickness control; Thickness measurement; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology, 1999. IEEE International Conference
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-5174-6
Type
conf
DOI
10.1109/IITC.1999.787092
Filename
787092
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