Title :
A low redeposition rate high density plasma CVD process for high aspect ratio 175 nm technology and beyond
Author :
Lee, G.Y. ; Ivers, T.H. ; Papasouliotis, G.D. ; Kiewra, E.W. ; Ning, X.J. ; Van Schravendijk, B.J.
Author_Institution :
Siemens Microelectron. Inc., Hopewell Junction, NY, USA
Abstract :
As aluminum reactive ion etch (RIE) technology extends to sub-0.20 μm technology, a void-free back-end-of-line (BEOL) gap-fill process is one of the major challenges for interconnects. When a stitched word line architecture is employed, the first metal wiring level often follows the minimum ground rule (GR). To maintain low sheet resistance, the aluminum line height cannot be significantly reduced. Therefore, the aspect ratio of current spaces is well over 2.5 and will approach 4.5 with future lithography shrinkages. Deposition temperature constraints make BEOL gap-fill much harder than front-end-of-line (FEOL), where such high aspect ratios are routinely filled. In this paper, a low redeposition rate high density plasma chemical vapor deposition (HDP-CVD) process has been developed at low deposition temperature to fill beyond 3.0 to 1 aspect ratio without void formation
Keywords :
aluminium; encapsulation; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; passivation; plasma CVD; plasma density; sputter etching; voids (solid); 0.2 micron; Al RIE technology; Al-SiO2; BEOL gap-fill; HDP-CVD process; aluminum line height; aluminum reactive ion etch technology; aspect ratio; current space aspect ratio; deposition temperature; deposition temperature constraints; first metal wiring level; front-end-of-line gap fill; high density plasma CVD process; interconnects; lithography shrinkage; minimum ground rule; redeposition rate; sheet resistance; stitched word line architecture; void formation; void-free back-end-of-line gap-fill process; Aluminum; Chemical vapor deposition; Etching; Land surface temperature; Lithography; Plasma applications; Plasma chemistry; Plasma density; Plasma temperature; Wiring;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787106
