DocumentCode :
3085418
Title :
Cost and delay tradeoff in three-stage switch architecture for data center networks
Author :
Shu Fu ; Bin Wu ; Xiaohong Jiang ; Pattavina, A. ; Lei Zhang ; Shizhong Xu
Author_Institution :
Sch. of Comput. Sci. & Technol., Tianjin Univ., Tianjin, China
fYear :
2013
fDate :
8-11 July 2013
Firstpage :
56
Lastpage :
61
Abstract :
Data center networks (DCNs) generally adopt Clos network with crossbar middle switches to achieve non-blocking data switching among the servers, and the number of middle switches is proportional to the number of ports of the aggregation switches in a fixed manner. Besides, reconfiguration overhead of the switches is generally ignored, which may contradict the engineering practice. In this paper, we consider batch scheduling based packet switching in DCNs with reconfiguration overhead at each middle switch, which inevitably leads to packet delay. With existing state-of-the-art traffic matrix decomposition algorithms, we can generate a set of permutations, each of which stands for the configuration of a middle switch. By reconfiguring each middle switch to fulfill multiple configurations in parallel with others, we reveal that a tradeoff exists between packet delay and switch cost (denoted by the number of middle switches), while performance guaranteed switching with bounded packet delay can be achieved without any packet loss. Based on the tradeoff, we can minimize the number of middle switches (under a given packet delay bound) and an overall cost metric (by translating delay into a comparable cost factor), as well as formulating criterions for choosing a matrix decomposition algorithm. This provides a flexible way to reduce the number of middle switches by slightly enlarging the packet delay bound.
Keywords :
computer centres; matrix algebra; packet switching; telecommunication traffic; DCN; cost tradeoff; crossbar middle switches; data center networks; delay tradeoff; nonblocking data switching; packet delay; packet delay bound; packet switching; state-of-the-art traffic matrix decomposition algorithms; switch cost; three-stage switch architecture; Delays; Matrix decomposition; Minimization; Optical switches; Ports (Computers); Servers; Clos network; Data center networks (DCNs); matrix decomposition; packet switching; scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Switching and Routing (HPSR), 2013 IEEE 14th International Conference on
Conference_Location :
Taipei
ISSN :
2325-5552
Type :
conf
DOI :
10.1109/HPSR.2013.6602290
Filename :
6602290
Link To Document :
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