Title :
Co-integration of InGaAs n- and SiGe p-MOSFETs into digital CMOS circuits using hybrid dual-channel ETXOI substrates
Author :
Czornomaz, L. ; Daix, N. ; Cheng, K. ; Caimi, D. ; Rossel, C. ; Lister, K. ; Sousa, M. ; Fompeyrine, J.
Author_Institution :
IBM Zurich Res. Lab., Zurich, Switzerland
Abstract :
We demonstrate for the first time a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI). We first show that such hybrid substrates can be fabricated by direct wafer bonding with stacked high-mobility layers thinner than 8nm. A process flow is presented that allows us to fabricate n- and p-channel field effect transistors with ultra-thin body and BOX (UTBB-FET) on the same wafer. Gate lengths down to 40nm produced at sub-μm gate-pitch are achieved. Working CMOS inverters are obtained using a common front-end which confirms the viability of this integration scheme for hybrid high-mobility dual-channel CMOS. We also highlight that back-biasing technique for Vt tuning can still be used despite the dualchannel structure, as implemented in standard ETSOI circuits.
Keywords :
CMOS digital integrated circuits; Ge-Si alloys; III-V semiconductors; MOSFET; elemental semiconductors; indium compounds; wafer bonding; CMOS inverters; InGaAs; SiGe; back biasing technique; common front end; coplanar nanoscaled nFET; coplanar nanoscaled pFET; digital CMOS circuits; direct wafer bonding; extremely thin layers on insulators; hybrid dual channel ETXOI substrates; pMOSFET; stacked high mobility layers; CMOS integrated circuits; Indium gallium arsenide; Inverters; Logic gates; Silicon; Silicon germanium; Substrates;
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.2013.6724548