Copper-SilK integration in a 0.18 μm double level metal interconnect

Author

Demolliens, O. ; Berruyer, P. ; Morand, Y. ; Tabone, C. ; Roman, A. ; Cochet, M. ; Assous, M. ; Feldis, H. ; Blanc, R. ; Tabouret, E. ; Louis, D. ; Arvet, C. ; Lajoinie, E. ; Gobil, Y. ; Passemard, G. ; Jourdan, F. ; Moussavi, M. ; Cordeau, M. ; Morel, T.

Author_Institution

CEA, Centre d´´Etudes Nucleaires de Grenoble, France

fYear

1999

fDate

1999

Firstpage

198

Lastpage

199

Abstract

This paper describes the integration of copper and SilK in a 0.18 μm DLM interconnect. The main integration issues such as dual damascene patterning, SilK porosity and copper filling have been addressed, as shown by the 0.5 Ω-100% yield obtained for 0.3 μm vias. The Cu/SilK interest is confirmed by a 40% RC reduction compared to a Cu-SiO₂ structure

Keywords

copper; delays; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; permittivity; porosity; 0.18 micron; 0.3 micron; 0.5 ohm; Cu; Cu-SiO₂; Cu-SiO₂ structure; DLM interconnect; RC delay reduction; SilK low-k dielectric; SilK porosity; copper filling; copper-SilK integration; double level metal interconnect; dual damascene patterning; via yield; Cleaning; Copper; Degradation; Electrical resistance measurement; Etching; Filling; Lithography; Metallization; Temperature measurement; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology, 1999. IEEE International Conference

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-5174-6

Type

conf

DOI

10.1109/IITC.1999.787121

Filename

787121