New interconnect capacitance characterization method for multilevel metal CMOS processes

Author

Froment, B. ; Guichard, E. ; Borot, B. ; Cluzel, Jacques ; Schoellkopf, J.-P. ; Jaouen, H.

Author_Institution

STMicroelectron., Crolles

fYear

1999

fDate

1999

Firstpage

224

Lastpage

226

Abstract

In this paper, a new method (ARPIC: automatic representation of patterns for interconnect characterization) of interconnect capacitance characterization is shown. ARPIC is a matrix of 1606 patterns containing the most frequent capacitive loads existing in a design. Its main purpose is to calibrate a simulator. A very good fit is obtained between measurements and simulation for a state-of-the-art 0.18 μm CMOS process with low-k dielectric, and we demonstrate that the ARPIC method can characterize interconnect capacitance with 0.1 fF resolution

Keywords

CMOS integrated circuits; calibration; capacitance; circuit simulation; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; integrated circuit modelling; ARPIC method; ARPIC pattern matrix; CMOS process; IC measurements; IC simulation; automatic representation of patterns for interconnect characterization; capacitive loads; interconnect capacitance; interconnect capacitance characterization; interconnect capacitance characterization method; low-k dielectric; multilevel metal CMOS processes; simulator calibration; CMOS process; CMOS technology; Capacitance measurement; Circuit simulation; Circuit testing; Current measurement; Driver circuits; Integrated circuit interconnections; Parasitic capacitance; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology, 1999. IEEE International Conference

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-5174-6

Type

conf

DOI

10.1109/IITC.1999.787128

Filename

787128