Etching and stripping process developments for sub-10nm FDSOI device architectures using alternative lithography techniques

To meet CD specifications required for 10nm and beyond Fully-depleted SOI devices (FDSOI) techniques alternative to EUV lithography are being developed. This article reports on the demonstration of Self-Aligned Dual Patterning (SADP), multi-beam electronic lithography and Directed Self-Assembly (DSA) to fabricate silicon fins with width <; 10nm and high-k / metal gates with 11nm CD, or to shrink contacts down to 15nm diameter. For such small dimension devices, minimizing material loss of the etch stop layers is also a major concern that needs to be stringently controlled. A process combining material modification by light ions plasma implantation and selective wet removal of the modified layer was demonstrated to achieve very low source / drain SiGe recess in spacer etching, which results are shown in this article.