Title :
A fully integrated pillar process for high performance Cu interconnect scheme
Author :
Kajita, Akihiro ; Higashi, Kazuyuki ; Matsunaga, Noriaki ; Shibata, Hideki
Author_Institution :
ULSI Process Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
A novel back-end of the line process for sub-quarter micron high performance devices, which is called the pillar process, has been proposed. The main features of the process is to form aluminum pillars as via plugs. Compared with the conventional metal plug process, the fine via opening process and complicated cleaning at the via interface are not required. By combining the pillar with a Cu single-damascene process, excellent electrical characteristics such as 20% lower wire resistance and 30% lower via resistance than that of conventional Cu dual-damascene structures have been obtained
Keywords :
aluminium; copper; electric resistance; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; integrated circuit testing; Cu dual-damascene structures; Cu interconnect scheme; Cu single-damascene process; Cu-Al; aluminum pillars; back-end of line process; device performance; electrical characteristics; fine via opening process; integrated pillar process; metal plug process; pillar process; via interface cleaning; via plugs; via resistance; wire resistance; Aluminum; Cleaning; Copper; Electric resistance; Electric variables; Plugs; Silicon compounds; Sputter etching; Sputtering; Wire;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787138
