DocumentCode :
3085973
Title :
Design options for hetero-junction tunnel FETs with high on current and steep sub-threshold voltage slope
Author :
Brocard, Sylvan ; Pala, Marco G. ; Esseni, David
Author_Institution :
IMEP-LAHC, Grenoble INP, Grenoble, France
fYear :
2013
fDate :
9-11 Dec. 2013
Abstract :
This work presents a systematic design study of nanowire Tunnel-FETs at LG=17nm employing a 3D Poisson-NEGF solver based on a 8×8 k·p Hamiltonian and including phonon scattering. In particular: (a) we revisit the design of GaSb-InAs based hetero-junction tunnel-FETs showing that this system is unlikely to yield a broken bangap profile at the very narrow features necessary for a good sub-VT slope value; (b) we propose new design options for hetero-junction tunnel-FETs, relying on the use of strain and of a graded molar fraction (xM) in AlxMGa(1-xM)Sb, which improve remarkably on current preserving optimal sub-VT slopes; (c) we show that interface defects can frustrate any design strategy aiming at sub-VT slope values below 60mV/dec.
Keywords :
III-V semiconductors; MOSFET; Poisson equation; aluminium compounds; gallium compounds; indium compounds; nanowires; semiconductor heterojunctions; tunnel transistors; 3D Poisson-NEGF solver; AlGaSb; GaSb-InAs; graded molar fraction; heterojunction tunnel FET; interface defects; nanowire tunnel-FET; phonon scattering; subthreshold voltage slope; Logic gates; MOSFET; Phonons; Tensile strain;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
Type :
conf
DOI :
10.1109/IEDM.2013.6724567
Filename :
6724567
Link To Document :
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