Title :
Scaling effect on electromigration in on-chip Cu wiring
Author :
Hu, C.-K. ; Rosenberg, R. ; Rathore, H.S. ; Nguyen, D.B. ; Agarwala, B.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Electromigration in on-chip plated Cu damascene interconnections has been investigated for metal line widths from 0.24 μm to 1.3 μm. Void growth at the cathode end and protrusions at the anode end of the lines have been found to be the main causes of failure. The failure lifetime was found to decrease linearly with decrease in the cross-sectional area of the line. This behavior can be explained by interface diffusion as the dominant path for transport and by the bamboo-like nature of the microstructure. The factor of n for the lifetime dependence on current density for 0.28 μm wide lines, τ=τ0j-n, was found to increase from 1 to 2 as j increased beyond 25 mA/μm2
Keywords :
copper; current density; diffusion; electromigration; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; surface chemistry; voids (solid); 0.24 to 1.3 micron; 0.28 micron; Cu; anode end protrusions; bamboo-like microstructure; cathode end void growth; dominant transport path; electromigration; failure causes; failure lifetime; interface diffusion; lifetime current density dependence; line cross-sectional area; metal line width; on-chip Cu wiring; on-chip plated Cu damascene interconnections; scaling effect; void growth; Anodes; Cathodes; Circuit testing; Dielectrics; Electromigration; Etching; Log-normal distribution; Microelectronics; System testing; Wiring;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787140
