DocumentCode
3086039
Title
Damascene process induced charging damage phenomenon
Author
Matsunaga, Noriaki ; Yoshinari, Hitomi ; Tomioka, Kazuhiro ; Shibata, Hideki
Author_Institution
Lab. of Microelectron. Eng., Toshiba Corp., Tokyo, Japan
fYear
1999
fDate
1999
Firstpage
276
Lastpage
278
Abstract
Performance degradation of MOSFETs due to plasma charging damage in a damascene interconnect process was evaluated in contrast to the conventional interconnect process which utilizes reactive ion etching (RIE) for metal patterning. Greater MOSFET performance degradation was observed in the damascene interconnect process than that in the metal RIE based interconnect process, notwithstanding the process where devices were directly exposed to plasma was reduced. It is considered that the degradation is due to the discharge current of charges which are charged up in the interconnect trench during the trench RIE process. A two step etching process using an etch stopper on metal was confirmed to reduce the charging damage
Keywords
MOS integrated circuits; MOSFET; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; plasma materials processing; sputter etching; MOSFET performance degradation; MOSFETs; RIE; charging damage; damascene interconnect process; damascene process induced charging damage phenomenon; discharge current; etch stopper; interconnect process; interconnect trench charge build-up; metal RIE based interconnect process; metal patterning; plasma charging damage; reactive ion etching; trench RIE process; two step etching process; Argon; Degradation; Dielectrics; Etching; MOSFETs; Microelectronics; Plasma applications; Plasma devices; Protection; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology, 1999. IEEE International Conference
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-5174-6
Type
conf
DOI
10.1109/IITC.1999.787143
Filename
787143
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