• DocumentCode
    3086058
  • Title

    Extracting a planar spanning subgraph of a terminal-vertex graph by solving the independent set problem

  • Author

    Yamaoki, Tsutomu ; Taoka, Satoshi ; Watanabe, Toshimasa

  • Author_Institution
    Fac. of Eng., Hiroshima Univ., Japan
  • Volume
    5
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    153
  • Abstract
    This paper proposes four heuristic algorithms MISi (i=1,2,3,4) for extracting a spanning planar subgraph from a given terminal-vertex graph, in which a path or a directed cycle represents how pins of a given element of electrical circuits are located, and a net does connection requirement among pins. Extracting a largest possible planar spanning subgraph of a terminal-vertex graph has application to layout design of printed wiring boards or of VLSI. Experimental results show that all of the proposed algorithms outperform the existing one MNC, which has been showing the highest capability, and that MIS3 or MIS4 gives the best performance among them
  • Keywords
    circuit layout CAD; graph theory; set theory; MIS; VLSI; electrical circuit; heuristic algorithm; independent set problem; layout design; planar spanning subgraph; printed wiring board; terminal vertex graph; Circuits and systems; Clocks; Erbium; Facsimile; Heuristic algorithms; Pins; Systems engineering and theory; Tree graphs; Very large scale integration; Virtual reality;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
  • Conference_Location
    Sydney, NSW
  • Print_ISBN
    0-7803-6685-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2001.922008
  • Filename
    922008