Optimization of damascene feature fill for copper electroplating process

Author

Reid, J. ; Bhaskaran, V. ; Contolini, R. ; Patton, E. ; Jackson, R. ; Broadbent, E. ; Walsh, T. ; Mayer, S. ; Schetty, R. ; Martin, J. ; Toben, M. ; Menard, S.

Author_Institution

Portland Technol. Center, Novellus Syst., Wilsonville, OR, USA

fYear

1999

fDate

1999

Firstpage

284

Lastpage

286

Abstract

A copper electroplating process suitable for routine IC manufacturing use must deliver Cu films that reproducibly fill deep, narrow damascene features. In this paper, several important factors such as seed layer coverage, plating waveform (DC, reversed-pulse), and additive chemistry formulation were examined in terms of their effect on the elimination of localized void defects within filled structures. A combination of two-step DC plating and custom additive chemistry enabling complete fill of 9:1 aspect ratio (AR), 0.13 μm trenches and 5:1 AR, 0.18 μm vias was accomplished

Keywords

circuit optimisation; copper; electroplating; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; surface chemistry; voids (solid); 0.13 micron; 0.18 micron; Cu; Cu films; DC plating waveform; IC manufacturing; additive chemistry formulation; copper electroplating process; custom additive chemistry; damascene feature fill optimization; damascene features; filled structures; localized void defects; reproducible damascene feature filling; reversed-pulse plating waveform; seed layer coverage; trench aspect ratio; two-step DC plating; via aspect ratio; Additives; Artificial intelligence; Chemical technology; Chemistry; Copper; Fabrication; Filling; IEEE news; Manufacturing processes; Neck;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology, 1999. IEEE International Conference

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-5174-6

Type

conf

DOI

10.1109/IITC.1999.787145

Filename

787145