Title :
Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits
Author :
Bobba, Sudhakar ; Hajj, Ibrahim N.
Author_Institution :
Sun Microsyst. Inc., Palo Alto, CA, USA
Abstract :
In this paper, we present techniques to find an input vector that maximizes the intrinsic decoupling capacitance of a circuit. This input vector can be used to enhance the on-chip decoupling capacitance in the standby mode and when the macroblock is not used or disabled by certain applications. Enhancing the decoupling capacitance increases the effective charge stored on chip and also makes the power bus stiffer. This can reduce the voltage variations at nodes in the power distribution network. A genetic-algorithm-based technique and a guided randomized search with look-ahead-based technique are used to generate the input vector. Experimental results for the ISCAS85 benchmark circuits are also presented
Keywords :
VLSI; capacitance; circuit CAD; circuit optimisation; genetic algorithms; integrated circuit design; search problems; ISCAS85 benchmark circuits; VLSI circuits; genetic-algorithm-based technique; guided randomized search; input vector generation; look-ahead-based technique; maximum intrinsic decoupling capacitance; onchip decoupling capacitance; power distribution network; standby mode; Clocks; Integrated circuit interconnections; Logic; Parasitic capacitance; Power supplies; Power systems; Space exploration; Sun; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922018
