Title :
A design of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms expression
Author :
Tsutsui, Hiroshi ; Hiwada, Kazuhiro ; Izumi, Tomonori ; Onoye, Takao ; Nakamura, Yoshihiko
Author_Institution :
Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
Abstract :
In this paper, an architecture of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms (SGCTs) expression are proposed. We formulate logic synthesis and layout for the LUT array into SGCT minimization so that the SGCT approach successfully merges these two synthesis stages. An SGCT generation procedure from an incompletely specified function is also presented. Experimental results demonstrate that the numbers of terms needed by our approach to map benchmark circuits into 2-LUT arrays and 3-LUT arrays are reduced to 70.7% and 85.1% on average of those by the existing approach, respectively
Keywords :
circuit CAD; circuit layout CAD; logic CAD; minimisation of switching nets; programmable logic arrays; table lookup; LUT-array-based PLD design; SGCT generation procedure; incompletely specified function; logic layout; logic synthesis; lookup table; minimization; sum of generalized complex terms expression; synthesis method; Boolean functions; Circuit synthesis; Computer architecture; Design engineering; Electronic mail; Logic arrays; Logic devices; Minimization; Programmable logic arrays; Table lookup;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922020
