Title :
Power constrained test scheduling using power profile manipulation
Author :
Rosinger, P.M. ; Al-Hashimi, Bashir M. ; Nicolici, Nicola
Author_Institution :
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
Abstract :
This paper presents a novel power profile manipulation technique which improves the test application time of existing power constrained test scheduling algorithms. This is achieved by test sequence reordering and rotation combined with a new power approximation model. Experiments using benchmark circuits show that use of this technique can lead to savings up to 25% in test time
Keywords :
failure analysis; fault diagnosis; integrated circuit testing; logic testing; low-power electronics; scheduling; benchmark circuits; power approximation model; power constrained test; power profile; savings; test scheduling algorithms; test sequence reordering; Benchmark testing; CMOS technology; Circuit noise; Circuit testing; Concurrent computing; Job shop scheduling; Manufacturing; Power dissipation; Scheduling algorithm; System testing;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922032
