Title :
An AVPG for SOC design verification with port order fault model
Author :
Wang, Chun-Yao ; Tung, Shing-Wu ; Jou, Jing-Yang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Embedded cores are being increasingly used in the design of large system-on-a chip (SoC). Because the high complexity of SoC, the design verification is a challenge for system integrator. To reduce the verification complexity, the port order fault (POF) model has been used for verifying the core-based design. In this paper, we present a verification scheme and an automatic verification pattern generation (AVPG) system based on POF model
Keywords :
automatic test pattern generation; fault diagnosis; integrated circuit design; integrated circuit testing; AVPG; POF model; SOC design verification; automatic verification pattern generation; design verification; embedded cores; heuristic verification; port order fault model; system-on-a chip; verification complexity; Adders; Availability; Circuit faults; Cost function; Design engineering; Design methodology; Integrated circuit interconnections; Manufacturing; System-on-a-chip; Testing;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922034
