A hybrid morphology processing units architecture for real-time video segmentation systems

Author

Chien, Shno-Yi ; Huang, Yu-Wen ; Ma, Shyh-Yih ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

5

fYear

2001

fDate

2001

Firstpage

275

Abstract

In this paper, we propose a hybrid morphology processing units architecture for real-time video segmentation systems. It contains two parts: a gray-level part and a binary part. A partial-result-reuse technique is applied to reduce the hardware cost of gray-level part. For the target of high throughput and flexibility, the binary part is implemented with a programmable PE array. Simulation shows the proposed hardware architecture is efficient in both hardware complexity and memory organization

Keywords

digital signal processing chips; image segmentation; mathematical morphology; real-time systems; video signal processing; binary part; gray-level part; hardware architecture; hardware complexity; hybrid morphology processing units architecture; memory organization; partial-result-reuse technique; programmable PE array; real-time video segmentation systems; throughput; Background noise; Change detection algorithms; Costs; Filters; Hardware; Morphological operations; Morphology; Noise cancellation; Real time systems; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922038

Filename

922038