CeNSE: A central nervous system for the earth

Moore´s Law and the scaling of microelectronics is expected to extend to 11 nm and most probably beyond. The key challenges are lithography, and fitting the device and the interconnect into a shrinking footprint. In this paper, challenges on device will be highlighted (short channel effects, leakage, threshold and auxiliary device requirements), and interconnect (RC trends, and reliability challenges). This also address the challenges faced because of high power density. Some of these challenges may force the industry to adopt radical changes in device and/or interconnect.