Temperature-dependent characteristics of diffused and polysilicon resistors for ULSI applications

Author

Uang, Chii-Maw ; Chuang, Hung-Ming ; Shen -Fu, T. ; Thei, Kong-Beng ; Lai, Po-Hsien ; Fu, Ssu-I ; Tsai, Shen Fu ; Wen-Chau Liu

Author_Institution

Dept. of Electr. Eng., I Shou Univ., Kaohsiung, Taiwan

fYear

2004

fDate

15-16 March 2004

Firstpage

293

Lastpage

296

Abstract

The temperature-dependent characteristics of polysilicon and diffused resistors have been studied. By using the 0.18 μm CMOS technology, cobalt salicide process is employed and silicide is formed at the ends of resistors. Based on a simple and useful model, some important parameters of resistors including bulk sheet resistance (R_bulk) and interface resistance (R_interface) are obtained at different temperature. For diffused resistors, the R_bulk and R_interface, values are increased and decreased with the increase of temperature, respectively. Positive values of temperature coefficient of resistance (TCR) are observed. Furthermore, TCR values are decreased with the decrease of resistor size. For polysilicon resistors, the Rinterface values are decreased with the increase of temperature. In addition, negative and positive TCR values of RNA are found in n⁺ and p⁺ polysilicon resistors, respectively. In conclusion, by comparing the studied diffused and polysilicon resistors, the negative trends of TCR are observed when the resistor sizes are decreased.

Keywords

CMOS integrated circuits; ULSI; chemical interdiffusion; chemical mechanical polishing; contact resistance; elemental semiconductors; etching; isolation technology; planarisation; rapid thermal annealing; resistors; silicon; CMOS technology; Si; ULSI; bulk sheet resistance; chemical mechanical polish; cobalt salicide process; diffused resistors; interface resistance; metallization process; planar process; polysilicon resistors; positive temperature coefficient of resistance; rapid thermal annealing; resistor size; resistor-protect-oxide layer; shallow trench isolation; temperature-dependent characteristics; via-hole etching; CMOS process; CMOS technology; Circuits; Implants; Microelectronics; Resistors; Silicides; Silicon; Temperature; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2004. IWJT '04. The Fourth International Workshop on

Print_ISBN

0-7803-8191-2

Type

conf

DOI

10.1109/IWJT.2004.1306860

Filename

1306860