FGMOS four-quadrant analog multiplier

This paper presents a four-quadrant analog multiplier. The architecture of the multiplier is designed with floating-gate CMOS transistors formed by squaring and current mirrors circuits. The results shown are accurate and appropriate. It is based on the square-law dependence of the MOS-transistor drain current on the gate-to-source voltage. To demonstrate the relevance of the design, aspect rations of the transistors is taken into account such that all the transistors are operating in saturation region. Also, in order to provide a linear behavior for the multiplier, the proposed design, present benefits in terms of linearity, threshold voltage mismatch, bandwidth, dynamic range and low power and low voltage. The multiplier is designed for SCN 0.13μm technology, the power supply is 0.5V and the power consumption is 1.56μW.