Title :
Modified standard cell methodology for VLSI layout compaction
Author :
Chavez-Martinez, E.J. ; Chavez-Martinez, M. ; Gurrola-Navarro, M.A.
Abstract :
A modification of the standard cell methodology to obtain area reduction in synthesized digital system layouts is presented. The proposed modifications consist in the full-custom redesign of the standard cell library and the application of a compaction algorithm in the step of cell placement. The effectiveness of the methodology has been shown compacting the cores of four digital systems. In the test were obtained reductions 22% minimum with a minimal increase in computational time.
Keywords :
VLSI; integrated circuit design; VLSI layout compaction; area reduction; cell placement; standard cell library; standard cell methodology; synthesized digital system layout; Compaction; Computer architecture; Layout; Libraries; Microprocessors; Standards; Transistors; CAD; EDA; VLSI; algorithm; compaction; layout; place-and-route; pull-down-network; pull-up-network; synthesis;
Conference_Titel :
Electrical Engineering, Computing Science and Automatic Control (CCE), 2012 9th International Conference on
Conference_Location :
Mexico City
Print_ISBN :
978-1-4673-2170-9
DOI :
10.1109/ICEEE.2012.6421201
