DocumentCode
3086905
Title
Deep sub-micron ultra-low power CMOS device design and optimization
Author
Liu, Xinfu ; Wu, K.Y. ; Ju, Jianghua ; Ho, Hokmin ; Yu, Xing ; Chen, Steven
Author_Institution
Serydconductor Manuf. Int. Corp., Shanghai, China
fYear
2004
fDate
15-16 March 2004
Firstpage
328
Lastpage
330
Abstract
In this work, CMOS devices with very low leakage current (Ioff) are studied for Ultra Low Power (ULP) applications. The ULP is targeted for worst-case Ioff <0.5 pA/μm. We used our 0.15 μm and 0.18 μm base line process to optimize the Vt, LDD, pocket and S/D implant to reduce device GIDL, poly edge junction leakage, band to band leakage and DIBL. A ULP product, CMOS I Mbit SRAM with measured minimum standby current < 10 μA were fabricated successfully.
Keywords
CMOS memory circuits; SRAM chips; leakage currents; low-power electronics; CMOS SRAM; CMOS devices; DIBL; GIDL; band to band leakage; deep submicron device design; dynamic power consumption; low power consumption; poly edge junction leakage; static power consumption; subthreshold behavior; ultralow power; very low leakage current; CMOS technology; Current measurement; Design optimization; Energy consumption; Implants; Leakage current; MOSFET circuits; Random access memory; Semiconductor device manufacture; Short circuit currents;
fLanguage
English
Publisher
ieee
Conference_Titel
Junction Technology, 2004. IWJT '04. The Fourth International Workshop on
Print_ISBN
0-7803-8191-2
Type
conf
DOI
10.1109/IWJT.2004.1306872
Filename
1306872
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