Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation

Application-specific instruction-set extension of an extensible processor is an effective way of improving the performance of a system. However, identifying an optimum instruction-set extension for a target application is a difficult problem. In this paper, we propose a novel approach to automatic identification of instruction-set extensions by combining branch and bound and high-level synthesis techniques. The approach allows adding instructions containing memory operations, improving the system performance significantly. We also propose an alias aware multi-port data cache architecture, which helps memory operation inclusive instructions get better performance by making them respond to multiple requests at the same cycle. Experimental result shows that the proposed approach improves the performance up to 3 times compared to the previous approaches.