A multiple-valued logic array VLSI based on two-transistor delta literal circuit and its application to real-time reasoning systems

Author

Hanyu, Takahiro ; Kojima, Yasushi ; Higuchi, Tatsuo

Author_Institution

Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan

fYear

1991

fDate

26-29 May 1991

Firstpage

16

Lastpage

23

Abstract

A multiple-valued logic array VLSI for high-speed pattern matching is presented. Both input data and rules are represented by a single multiple-valued digit, so that pattern matching can be described by a multiple-valued delta-literal, in which thresholds correspond to content of a rule. Moreover, a multiple-valued pattern-matching cell can be implemented by only a pair of an NMOS and a PMOS transistors whose threshold voltages are programmed by multiple ion implants. It is demonstrated that the chip area and power dissipation of 8-valued logic array can be reduced to 30% and 50%, respectively, compared with corresponding binary implementation

Keywords

CMOS integrated circuits; VLSI; computerised pattern recognition; logic arrays; many-valued logics; real-time systems; threshold elements; 8-valued logic array; NMOS transistors; PMOS transistors; VLSI; chip area; multiple ion implants; multiple-valued delta-literal; multiple-valued digit; multiple-valued logic array; multiple-valued pattern-matching cell; pattern matching; power dissipation; real-time reasoning systems; thresholds; two-transistor delta literal circuit; Implants; Logic arrays; Logic circuits; MOS devices; MOSFETs; Pattern matching; Power dissipation; Production systems; Real time systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1991., Proceedings of the Twenty-First International Symposium on

Conference_Location

Victoria, BC

Print_ISBN

0-8186-2145-1

Type

conf

DOI

10.1109/ISMVL.1991.130699

Filename

130699