Title :
Increase in delay uncertainty by performance optimization
Author :
Hashimoto, Masanori ; Onodeva, H.
Author_Institution :
Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
Abstract :
This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e., the delay of long paths are shortened and the delay of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which are caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statistically-distributed circuit delay
Keywords :
VLSI; circuit optimisation; delay estimation; digital integrated circuits; integrated circuit design; statistical analysis; VLSI design; circuit delay uncertainty increase; delay calculation error; delay constraints; manufacturing variability; operating condition fluctuation; path-balanced circuits; performance optimization; statistical characteristic; statistical effect; statistically-distributed circuit delay; Circuits; Delay effects; Fluctuations; Manufacturing; Optimization; Propagation delay; Timing; Uncertainty; Very large scale integration; Wire;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922064