Automatic clock tree design with IPs in the system

Author

Li, Wei ; Zhou, Diam ; Kim, Haksu ; Zeng, Xuan

Author_Institution

Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA

Volume

5

fYear

2001

fDate

2001

Firstpage

387

Abstract

A clock distribution methodology is presented for realizing the prespecified clock arriving time often occurring in the reusable block based design environment. In this strategy, not only the planar clock routing and buffer insertion are carried out simultaneously to minimize the total wire length and the clock skew, a full waveform simulation is used to ensure the signal integrity necessary for high-speed VLSI. Our experimental results demonstrate that the proposed method achieves a good circuit performance

Keywords

VLSI; circuit layout CAD; clocks; high-speed integrated circuits; industrial property; integrated circuit layout; network routing; wiring; IPs; automatic clock tree design; buffer insertion; circuit performance; clock distribution methodology; clock skew; full waveform simulation; high-speed VLSI; planar clock routing; prespecified clock arriving time; reusable block based design environment; signal integrity; total wire length; Circuit simulation; Clocks; Computational modeling; Delay effects; Delay estimation; Frequency; Integrated circuit interconnections; Routing; SPICE; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922066

Filename

922066