Title :
Energy efficient signaling in DSM CMOS technology
Author :
Dhaou, Imed Berz ; Tenhunen, Harzizu ; Sundararajan, V. ; Parhi, Keshab K.
Author_Institution :
Electron. Syst. Design Lab., R. Inst. of Technol., Kista, Sweden
Abstract :
The problem of efficient signaling over on-chip interconnect in DSM technology is addressed. A signaling scheme based on low-swing combined with repeater insertion and resizing is derived for both cascaded inverters and inverter chains. The proposed scheme has been implemented in 0.25 μm 2.5 V, 6 metal layers CMOS process. HSPICE results showed that our scheme leads to a substantial energy-saving ratio without speed degradation
Keywords :
CMOS digital integrated circuits; SPICE; VLSI; integrated circuit design; integrated circuit interconnections; logic gates; logic simulation; low-power electronics; repeaters; 0.25 micron; 2.5 V; DSM CMOS technology; HSPICE results; cascaded inverters; energy efficient signaling; energy-saving ratio; inverter chains; on-chip interconnect; repeater insertion; resizing; signaling scheme; speed degradation; CMOS technology; Crosstalk; Degradation; Delay; Energy efficiency; Inverters; Parasitic capacitance; Repeaters; Voltage; Wires;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922072
